1. Field of the Invention
The present invention relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device formed by using such a semiconductor thin film. As for the semiconductor thin film, the invention particularly relates to a silicon film having crystallinity.
2. Description of the Related Art
The thin-film transistor (TFT) is typically known as the above-mentioned semiconductor device. A liquid crystal display device, an EL device, a CL device, and other devices can be constructed by using thin-film transistors.
A technique is known in which the active layer of a TFT is formed on a single crystal silicon film by using the SOI (silicon on insulator) technology. In view of the uniformity and the controllability, the thickness of the single crystal film needs to be 1 .mu.m or more. The energy band gap (hereinafter referred to simply as Eg) of a silicon film formed by using the SOI technology is about 1.1 eV, which is approximately equal to the bulk Eg of a single crystal silicon film.
For example, consider a case where as shown in FIG. 2A the active layer of a TFT formed by using the SOI technology consists of conductive layers (n-type layers 201 or p-type layers 202) and an I layer (intrinsic semiconductor layer) that constitutes the channel. In this case, the energy band is curved at the junctions to equalize the Fermi levels (indicated by broken lines in FIG. 2A), so that an energy difference occurs between the I layer 203 and the conductive layers 201 and 202.
In this case, since the energy difference between the I layer 203 and the conductive layers 201 or 202 is as small as about 0.5 eV, for instance, carriers are allowed to move relatively easily even when no voltage is applied to the gate electrode (no electric field state).
That is, in a graph of FIG. 2A in which the horizontal and vertical axes represent the gate voltage (Vg) and the source-drain current (Id), respectively, the threshold voltage of an Id-Vg characteristic 204 of an n-channel TFT is shifted to the negative side and that of an Id-Vg characteristic 205 of a p-channel TFT is shifted to the positive side, to establish a normally-on state.
A TFT whose electrical characteristic is normally on is a depletion-type TFT. That is, the depletion-type TFT has a feature that it is always in an on-state. Conversely, a TFT that is always in an off-state (normally off) is called an enhancement-type TFT. However, for the above-described reason, when it is intended to form a channel-forming region by an intrinsic semiconductor in a SOI structure, a resulting TFT is necessarily a depletion type.
Therefore, in order to form an enhancement-type TFT, the threshold voltage is controlled by implanting, into a channel-forming region 208, an impurity for imparting p-type conductivity (for n-type conductive layers 206) or an impurity for imparting n-type conductivity (for p-type conductive layers 207) as shown in FIG. 2B.
As a result, as shown in FIG. 2B, the energy difference between the I layer 208 and the conductive layers 206 or 207 is increased to about 0.7 eV, for instance, to form sufficiently high barriers for carrier movement. That is, since the threshold voltage of an Id-Vg characteristic 209 of an n-channel TFT is shifted to the positive side and that of an Id-Vg characteristic 210 of a p-channel TFT is shifted to the negative side, it is possible to establish a normally-off state.
As described above, when an enhancement-type TFT is formed by using the SOI technology, the prior art has some demerits as exemplified by a fact that it is necessary to implant an impurity into a channel region, which means increase of an ion implantation step.
Further, it is known that when the active layer is thick, the characteristics of a TFT are likely deteriorated by the punch-through phenomenon, the short channel effect, etc. It is reported that in order to solve this problem it is effective to decrease the thickness of the active layer. To this end, however, the thickness needs to be 500 .ANG. or less; it is very difficult to attain such a thin active layer by the SOI technology, as described above.